This relates to reducing delays arising from switching in electrical circuits. It is particularly useful in memory circuits and will be described in that context. However, it may also find application elsewhere.
It frequently is necessary to switch the circuits that are used to access the memory of a computer. For example, it is necessary to switch between the circuits that are used to write data into the memory and those that are used to read data from the memory. Often these circuits are also time-shared between different memories, which are commonly referred to as different ranks of memories. Such time-sharing also requires switching between the different ranks of memories.
When an electrical circuit is being switched, it becomes temporarily unusable for accurate signal transmission. Thus, there is a delay between the last valid data processed by the electrical circuit before switching and the first valid data after switching. This delay is commonly referred to as a bubble; and when the delay is on a bidirectional data bus, it is commonly referred to as a DQ bubble. Due to the demand for faster memory operations, there is a need to eliminate or reduce the size of the DQ bubbles.